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Before I start reviewing the new Clock Tuner for Ryzen, I would like to thank the Ryzen community for their patience and warm welcome to the project. The release of CTR 1.0 and 1.1 was not so smooth and many faced a number of problems and shortcomings that cannot be solved with a hotfix or patch. It turned out to be physically impossible to process such a number of requests. Therefore, despite all the difficulties, it was decided to create a new project in a fairly short time without proper support from giant companies. If at least some samples were provided (initial and mid-level processors), then there was no information support at all. Fortunately, there were people in the community who possessed valuable information and skills, thanks to which it was possible to translate all plans into reality. In particular, special thanks to Keaton Blomquist and Vadym Kosmin for their contribution to the development of CTR 2.0.
The potential of Zen 3
In addition to all of the above, there was another major event that added pleasant hassle and pushed back the release of CTR 2.0 – this is the long-awaited release of AMD processors with the Zen 3 microarchitecture. GHz, and sometimes even higher.
Everything the community asked for, the community finally got. But these were not all surprises.
I think some of you remember the information in the news feeds that the Ryzen processors with the Zen 3 microarchitecture got the ability to individually adjust the frequencies for the cores. At the time of release, this turned out to be a slightly different feature than the news, including myself, said – individual voltage control for the core, referred to as “Curve Optimization”.
To my surprise, there was no mention of active dLDO in the presentation slides at all. During the development of CTR, it was discovered that during the boost to all cores, each core receives its portion of voltage, depending on the individual silicon characteristics (FIT). Information about this wonderful architectural feature began to flicker at the time of the announcement of processors codenamed Cezanne, although it already existed in processors codenamed Renoir.
I can also note that AMD was able to overcome weak single-core boost or single-core boost with cores that had mediocre silicon characteristics and fault tolerance. That is, now the marking of the CPPC cores corresponded to reality and the SMU correctly uses the cores in low-threaded applications with maximum energy efficiency. At this moment, it may seem to you that everything is optimized or overclocked to you and us, enthusiasts, there is nothing more to do here, but this is not so.
The margin of “strength” of silicon, or as some call it “potential”, has not been canceled, since long-term testing of silicon in the factory means additional time and additional resources, which can ultimately lead to a disproportionate increase in the cost of the product. That is, there is a silicon testing template with certain tolerances (required range) for voltage relative to a certain frequency, according to which chips will be selected and, depending on this, they will fall into either Ryzen 7 5800X or Ryzen 9 5900X (for example). As a result, each CPU has a chance for a lottery, but processors with two CCDs have a greater chance of gaining performance. I’ll give you an example. The Ryzen 9 5900X and Ryzen 7 5800X processors have similar TDP and PPT, but have dramatically different performance. This suggests that the chips used in the Ryzen 9 5900X have the best frequency to voltage ratio and such processors tend to have huge overclocking potential. The Ryzen 9 5950X, on the other hand, has a better frequency-to-temperature ratio. In addition, the Ryzen 9 5900X and Ryzen 9 5950X processors have another interesting feature. CCD # 1 is always a super selective copy and in most cases it is this CCD that is able to conquer the 5GHz mark, while CCD # 2 is only a makeweight with an average binning category in order to reduce the cost of the final product and often it is CCD # 2 that we most often see as main CCD in Ryzen 5 5600X.
As for the technical process, it has been significantly improved. If earlier the generation of processors with the Zen 2 microarchitecture needed about 1.1 V to conquer the frequency of 4050 MHz, now for Zen 3 we can count on 4375 MHz at 1.1 V, that is, + 8%, while the static leakage currents have not changed much .
AMD has also taken care to eliminate the temperature peaks that were previously observed in idle mode for a significant proportion of owners of Zen 2 microarchitecture processors. Now the voltage can drop as low as 0.3 V, and short-term background activity of the operating system will no longer trigger a maximum performance state with a value of VID at 1.45V. Operating temperatures have not changed during load, but it is also recommended to use high-efficiency cooling, since boost and potential in CTR depend on this, while the difference can be about 300 MHz when comparing conventional air and custom water cooling.